Rst =1     Q=0
Clk=1     Q=d

kodingnya:

Library ieee;
Ieee.std_logic_1164.all;


Entity DFF is
Port (
D, clk, rst    : IN std_logic;
Q    : OUT std_logic );
END off;


ARCHITECTURE latihan of DFF IS
SIGNAL Q=t; t : std_logic;
BEGIN
IF rst = 0 then t<=0;
Else if clk=1 then t<=d;
END latihan;